AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
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3.4. Connecting the TSN and Drive-on-Chip Subsystems

When connected, the HPS can control the TSN drive-on-chip design. You connect them via shared memory mechanism.

Intel recommends three connections.

  1. Connect the port h2f-axi_master of the block hps_0 of the TSN subsystem to the one port of the sys_console_debug_ram block.
    1. Enable Dual_port access in the sys_console_debug_ram block.
      The first memory mapped slave port (s1) connects to the HPS. The second port (s2) connects to the Nios II soft processor. The drive-on-chip subsystem reads position, speed, configurations commands for the drives from this memory.
      Figure 25. Turn on Share memory Dual-port access
  2. Optionally, create a connection between the HPS and the FPGA DDR3 memory.
    1. Connect the h2f_axi_master master port of the HPS to the avl_0 port of the mem_if_ddr3_emif_0 (external memory interface).
      This connection allows the access to the drive-on-chip subsystem DDR3 memory from the HPS (from Linux)
  3. To expose some peripherals of the TSN subsystem to the JTAG chain, add a connection between port s0 (Avalon MM Slave) of the mm_bridge_0 (TSN subsystem) to the port master of the jtag_master block in the drive-on-chip subsystem.
    Figure 26. Qsys System
  4. Click Generate HDL.