B. Top-level Verilog HDL File Example
Shows an example of the top-level Verilog HDL file for the TSN Drive-on-Chip Design project. This file is the drive-on-chip top-level Verilog HDL file including TSN capabilities of the TTTech TSN IP..
module DOC_TANDEM_CVSX_NIOS_TSN (
input wire clk_50,
input wire clk_ddr3_100_p,
input wire global_reset_n,
input wire [1:0] button,
output wire [3:0] LED,
output wire SD_MCLK, // Sigma-delta ADC clock
output wire BOOST_DRV0_PWM_H, // DC-DC Converter
output wire BOOST_DRV0_PWM_L,
output wire BOOST_DRV1_PWM_H,
output wire BOOST_DRV1_PWM_L,
input wire REGEN_EN_N,
input wire BOOST_DRV0_CURRENT_MDAT,
input wire BOOST_DRV1_CURRENT_MDAT,
input wire DCBUS_CURRENT_MDAT,
input wire DCBUS_VOLTAGE_MDAT,
input wire INPUT_CURRENT_MDAT,
input wire INPUT_VOLTAGE_MDAT,
output wire BOOST_STATUS, // DC-DC Status LEDs
output wire REGEN_STATUS,
input wire DRV0_FAULTn, // Axis 0 inverter
output wire DRV0_EN_GATE_N,
output wire DRV0_EN_GATE_P,
output wire HSMC_DRV0_PWM_UH,
output wire HSMC_DRV0_PWM_UL,
output wire HSMC_DRV0_PWM_VH,
output wire HSMC_DRV0_PWM_VL,
output wire HSMC_DRV0_PWM_WH,
output wire HSMC_DRV0_PWM_WL,
input wire DRV0_QHR_U, // Axis 0 Quad/Hall/resolver
input wire DRV0_QHR_V,
input wire DRV0_QHR_W,
input wire DRV0_QR_A,
input wire DRV0_QR_B,
input wire DRV0_QR_Z,
output wire DRV0_SER_CLK, // Axis 0 Serial
input wire DRV0_SER_RX,
output wire DRV0_SER_TX,
output wire DRV0_SER_TX_EN,
output wire DRV0_RESOLVER_SSCS, // Axis 0 Resolver
output wire DRV0_RESOLVER_SCSB,
output wire DRV0_RESOLVER_INHB,
input wire DRV0_RESOLVER_ERRHLD,
output wire DRV0_RESOLVER_ERRSTB,
input wire DRV0_U_CURRENT_MDAT, // Axis 0 sigma-delta ADCs
input wire DRV0_U_VOLTS_MDAT,
input wire DRV0_V_CURRENT_MDAT,
input wire DRV0_V_VOLTS_MDAT,
input wire DRV0_W_CURRENT_MDAT,
input wire DRV0_W_VOLTS_MDAT,
input wire DRV1_FAULTn, // Axis 1 inverter
output wire DRV1_EN_GATE_N,
output wire DRV1_EN_GATE_P,
output wire HSMC_DRV1_PWM_UH,
output wire HSMC_DRV1_PWM_UL,
output wire HSMC_DRV1_PWM_VH,
output wire HSMC_DRV1_PWM_VL,
output wire HSMC_DRV1_PWM_WH,
output wire HSMC_DRV1_PWM_WL,
input wire DRV1_QHR_U, // Axis 1 Quad/Hall/resolver
input wire DRV1_QHR_V,
input wire DRV1_QHR_W,
input wire DRV1_QR_A,
input wire DRV1_QR_B,
input wire DRV1_QR_Z,
output wire DRV1_SER_CLK, // Axis 1 Serial
input wire DRV1_SER_RX,
output wire DRV1_SER_TX,
output wire DRV1_SER_TX_EN,
output wire DRV1_RESOLVER_SSCS, // Axis 1 resolver
output wire DRV1_RESOLVER_SCSB,
output wire DRV1_RESOLVER_INHB,
input wire DRV1_RESOLVER_ERRHLD,
output wire DRV1_RESOLVER_ERRSTB,
input wire DRV1_U_CURRENT_MDAT, // Axis 1 sigma-delta ADCs
input wire DRV1_U_VOLTS_MDAT,
input wire DRV1_V_CURRENT_MDAT,
input wire DRV1_V_VOLTS_MDAT,
input wire DRV1_W_CURRENT_MDAT,
input wire DRV1_W_VOLTS_MDAT,
output wire DRV_SCLK, // SPI control bus for inverter gate drivers
output wire DRV_SIMO,
input wire DRV_SOMI,
output wire DRV0_CSn,
output wire DRV1_CSn,
output wire VOLTAGE_FAULT, // Inverter Status LEDs
output wire CURRENT_FAULT,
input wire HSMC_PRSNTn,
output wire GPIO_0,
output wire [14:0]mem_a, //FPGA DDR3 memory
output wire [2:0] mem_ba,
output wire [0:0] mem_ck,
output wire [0:0] mem_ck_n,
output wire [0:0] mem_cke,
output wire [0:0] mem_cs_n,
output wire [3:0] mem_dm,
output wire [0:0] mem_ras_n,
output wire [0:0] mem_cas_n,
output wire [0:0] mem_we_n,
output wire mem_reset_n,
inout wire [31:0]mem_dq,
inout wire [3:0] mem_dqs,
inout wire [3:0] mem_dqs_n,
output wire [0:0] mem_odt,
input wire mem_oct_rzqin,
output wire enet_hps_gtx_clk, //HPS ethernet
output wire enet_hps_mdc,
inout wire enet_hps_mdio,
input wire enet_hps_rx_clk,
input wire enet_hps_rx_dv,
input wire [3:0] enet_hps_rxd,
output wire enet_hps_tx_en,
output wire [3:0] enet_hps_txd,
output wire sd_clk, //HPS-SD-Card-Flash
inout wire sd_cmd,
inout [3:0] sd_dat,
input wire uart_rx, //HPS-UART
output wire uart_tx,
inout wire i2c_scl_hps, //HPS-I2C
inout wire i2c_sda_hps,
output wire [14:0]ddr3_hps_a, // CV SOC dev kit HPS DDR3 pins
output wire [2:0] ddr3_hps_ba,
output wire ddr3_hps_ck,
output wire ddr3_hps_ck_n,
output wire ddr3_hps_cke,
output wire ddr3_hps_cs_n,
output wire ddr3_hps_ras_n,
output wire ddr3_hps_cas_n,
output wire ddr3_hps_we_n,
output wire ddr3_hps_reset_n,
inout wire [39:0]ddr3_hps_dq,
inout wire [4:0] ddr3_hps_dqs,
inout wire [4:0] ddr3_hps_dqs_n,
output wire ddr3_hps_odt,
output wire [4:0] ddr3_hps_dm,
input wire ddr3_hps_oct_rzqin,
// TSN Switch
output wire eth_mdio_tristate_0_mdio_mdc,
inout wire eth_mdio_tristate_0_mdio_mdio,
output wire enet_dual_resetn,
input wire deip_0_gmii_to_mii_0_mii_rx_clk,
input wire deip_0_gmii_to_mii_0_mii_rx_dv,
input wire [3:0] deip_0_gmii_to_mii_0_mii_rxd,
input wire deip_0_gmii_to_mii_0_mii_rx_er,
input wire deip_0_gmii_to_mii_0_mii_tx_clk,
output reg deip_0_gmii_to_mii_0_mii_tx_en,
output reg [3:0] deip_0_gmii_to_mii_0_mii_txd,
input wire deip_0_gmii_to_mii_1_mii_rx_clk,
input wire deip_0_gmii_to_mii_1_mii_rx_dv,
input wire [3:0] deip_0_gmii_to_mii_1_mii_rxd,
input wire deip_0_gmii_to_mii_1_mii_rx_er,
input wire deip_0_gmii_to_mii_1_mii_tx_clk,
output reg deip_0_gmii_to_mii_1_mii_tx_en,
output reg [3:0] deip_0_gmii_to_mii_1_mii_txd
);
// System
wire reset_n = global_reset_n;
wire pll_locked;
// Allow software to select routing of encoder interfaces to/from pins
// QEP has desicated pins so selection is not actually needed
wire [7:0] encoder_select;
wire sel0_endat = ~encoder_select[2] & ~encoder_select[1] & ~encoder_select[0]; //000
wire sel0_biss = ~encoder_select[2] & ~encoder_select[1] & encoder_select[0]; //001
wire sel0_rslvr = ~encoder_select[2] & encoder_select[1] & ~encoder_select[0]; //010
wire sel1_biss = ~encoder_select[5] & ~encoder_select[4] & ~encoder_select[3]; //000
wire sel1_endat = ~encoder_select[5] & ~encoder_select[4] & encoder_select[3]; //001
wire sel1_rslvr = ~encoder_select[5] & encoder_select[4] & ~encoder_select[3]; //010
wire DRV0_SER_CLK_BISS = 1'b0;
wire DRV0_SER_CLK_ENDAT = 1'b0;
wire DRV0_SER_CLK_RSLVR;
wire DRV0_SER_CLK_RSLVR_CTRL;
wire DRV0_SER_CLK_RSLVR_POSN;
wire DRV0_SER_TX_BISS = 1'b0;
wire DRV0_SER_TX_ENDAT = 1'b0;
wire DRV0_SER_TX_RSLVR;
wire DRV0_SER_TX_EN_ENDAT = 1'b0;
wire DRV1_SER_CLK_BISS = 1'b0;
wire DRV1_SER_CLK_ENDAT = 1'b0;
wire DRV1_SER_CLK_RSLVR;
wire DRV1_SER_CLK_RSLVR_CTRL;
wire DRV1_SER_CLK_RSLVR_POSN;
wire DRV1_SER_TX_BISS = 1'b0;
wire DRV1_SER_TX_ENDAT = 1'b0;
wire DRV1_SER_TX_RSLVR;
wire DRV1_SER_TX_EN_ENDAT = 1'b0;
// Resolver chip has independent slave selects for SPI input and output but only one SCK input.
// We cannot use a single SPI master with two chip selects as the two data registers are different
// lengths and require different clock phase. To get around this we use two SPI masters with idle
// clock state set to high and then AND the two clocks.
assign DRV0_SER_CLK_RSLVR = DRV0_SER_CLK_RSLVR_CTRL & DRV0_SER_CLK_RSLVR_POSN;
assign DRV1_SER_CLK_RSLVR = DRV1_SER_CLK_RSLVR_CTRL & DRV1_SER_CLK_RSLVR_POSN;
assign DRV0_SER_CLK = sel0_biss ? DRV0_SER_CLK_BISS
: sel0_endat ? DRV0_SER_CLK_ENDAT
: sel0_rslvr ? DRV0_SER_CLK_RSLVR : 1'b0;
assign DRV0_SER_TX = sel0_biss ? DRV0_SER_TX_BISS
: sel0_endat ? DRV0_SER_TX_ENDAT
: sel0_rslvr ? DRV0_SER_TX_RSLVR : 1'b0;
assign DRV0_SER_TX_EN = sel0_biss ? 1'b0
: sel0_endat ? DRV0_SER_TX_EN_ENDAT
: sel0_rslvr ? 1'b1 : 1'b0;
assign DRV1_SER_CLK = sel1_biss ? DRV1_SER_CLK_BISS
: sel1_endat ? DRV1_SER_CLK_ENDAT
: sel1_rslvr ? DRV1_SER_CLK_RSLVR : 1'b0;
assign DRV1_SER_TX = sel1_biss ? DRV1_SER_TX_BISS
: sel1_endat ? DRV1_SER_TX_ENDAT
: sel1_rslvr ? DRV1_SER_TX_RSLVR : 1'b0;
assign DRV1_SER_TX_EN = sel1_biss ? 1'b0
: sel1_endat ? DRV1_SER_TX_EN_ENDAT
: sel1_rslvr ? 1'b1 : 1'b0;
wire dclink_overvoltage;
wire dclink_undervoltage;
wire dclink_overcurrent;
wire dcin_undervoltage;
wire dcin_overvoltage;
wire dcin_overcurrent;
wire lvdcdc_oc_latch;
wire lvdcdc_ov_latch;
wire Overcurrent0;
wire Overcurrent1;
assign GPIO_0 = 0;
// Resolver I/O
wire [1:0] drive0_rslvr_pio_out;
wire [1:0] drive1_rslvr_pio_out;
assign DRV0_RESOLVER_ERRSTB = drive0_rslvr_pio_out[0];
assign DRV0_RESOLVER_INHB = drive0_rslvr_pio_out[1];
assign DRV1_RESOLVER_ERRSTB = drive1_rslvr_pio_out[0];
assign DRV1_RESOLVER_INHB = drive1_rslvr_pio_out[1];
wire oc_latch_led0;
wire ov_latch_led0;
wire oc_latch_led1;
wire ov_latch_led1;
wire dc_dc_fault;
wire dc_dc_on;
assign BOOST_STATUS = dc_dc_on;
assign REGEN_STATUS = ~REGEN_EN_N;
assign VOLTAGE_FAULT = lvdcdc_oc_latch;
assign CURRENT_FAULT = lvdcdc_ov_latch;
// Status LEDs on MAX10 dev kit
wire [4:0] led_pio;
assign LED[0] = oc_latch_led0 | ov_latch_led0;
assign LED[1] = oc_latch_led1 | ov_latch_led1;
assign LED[2] = dcin_overvoltage | dcin_undervoltage | dcin_overcurrent;
//assign LED[3] = dc_dc_fault;
assign LED[3] = pps;
//assign LED[4] = led_pio[0];
// Safe torque off interlock outputs
assign DRV0_EN_GATE_P = 1'b1;
assign DRV0_EN_GATE_N = 1'b0;
assign DRV1_EN_GATE_P = 1'b1;
assign DRV1_EN_GATE_N = 1'b0;
wire enc_stb0_n;
wire enc_stb1_n;
wire [1:0] gate_drive_spi_ss_n;
assign DRV0_CSn = gate_drive_spi_ss_n[0];
assign DRV1_CSn = gate_drive_spi_ss_n[1];
// MAX10 ADC threshold detection
assign dclink_overvoltage = 1'b0; // There is no output signal in Autonomous DC-DC-Converter block
assign dclink_undervoltage = 1'b0; // There is no output signal in Autonomous DC-DC-Converter block
// Retime to rising clock edge of the ethernet interfaces
wire deip_0_gmii_to_mii_0_mii_tx_en_i;
wire [3:0] deip_0_gmii_to_mii_0_mii_txd_i;
wire deip_0_gmii_to_mii_1_mii_tx_en_i;
wire [3:0] deip_0_gmii_to_mii_1_mii_txd_i;
always @(posedge deip_0_gmii_to_mii_0_mii_tx_clk)
begin
deip_0_gmii_to_mii_0_mii_tx_en <= deip_0_gmii_to_mii_0_mii_tx_en_i;
deip_0_gmii_to_mii_0_mii_txd <= deip_0_gmii_to_mii_0_mii_txd_i;
end
always @(posedge deip_0_gmii_to_mii_1_mii_tx_clk)
begin
deip_0_gmii_to_mii_1_mii_tx_en <= deip_0_gmii_to_mii_1_mii_tx_en_i;
deip_0_gmii_to_mii_1_mii_txd <= deip_0_gmii_to_mii_1_mii_txd_i;
end
DOC_TANDEM_CVSX_NIOS_TSN_QSYS u_doc (
.clk_50_in_clk (clk_50),
.clk_adc_out_clk (SD_MCLK),
.clk_ddr_in_clk (clk_ddr3_100_p),
.reset_n_reset_n (reset_n),
.pll_reset_reset (1'b0),
.io_in_buttons_export ({~HSMC_PRSNTn, 7'b0} | button),
.io_out_led_export (led_pio),
.lvmc_dclink_dspba_lvdcdc_gate_drive_gate_a_h (BOOST_DRV0_PWM_H),
.lvmc_dclink_dspba_lvdcdc_gate_drive_gate_a_l (BOOST_DRV0_PWM_L),
.lvmc_dclink_dspba_lvdcdc_gate_drive_gate_b_h (BOOST_DRV1_PWM_H),
.lvmc_dclink_dspba_lvdcdc_gate_drive_gate_b_l (BOOST_DRV1_PWM_L),
.lvmc_dclink_dspba_lvdcdc_fault_input_input_ov_fault (dcin_overvoltage ),
.lvmc_dclink_dspba_lvdcdc_fault_input_input_uv_fault (dcin_undervoltage ),
.lvmc_dclink_dspba_lvdcdc_fault_input_output_ov_fault (dclink_overvoltage ),
.lvmc_dclink_dspba_lvdcdc_fault_input_output_uv_fault (dclink_undervoltage ),
.lvmc_dclink_dspba_lvdcdc_fault_input_input_oc_fault (dcin_overcurrent),
.lvmc_dclink_dspba_lvdcdc_fault_input_output_oc_fault (dclink_overcurrent),
.lvmc_dclink_dspba_lvdcdc_bidir_en_n (REGEN_EN_N),
.lvmc_dclink_dspba_lvdcdc_fault_status_overcurrent (lvdcdc_oc_latch),
.lvmc_dclink_dspba_lvdcdc_fault_status_overvoltage (lvdcdc_ov_latch),
.lvmc_dclink_dspba_lvdcdc_fault_status_fault_sync (dc_dc_fault),
.lvmc_dclink_dspba_lvdcdc_dc_dc_status_dc_dc_on (dc_dc_on),
.lvmc_dclink_lvdcdc_fb_adc_sync_dat_i_phase_a (BOOST_DRV0_CURRENT_MDAT),
.lvmc_dclink_lvdcdc_fb_adc_sync_dat_i_phase_b (BOOST_DRV1_CURRENT_MDAT),
.lvmc_dclink_lvdcdc_fb_adc_sync_dat_v_out (DCBUS_VOLTAGE_MDAT),
.lvmc_dclink_dc_in_v_status_sync_dat (INPUT_VOLTAGE_MDAT),
.lvmc_dclink_dc_in_v_status_dc_link_enable (1'b1),
.lvmc_dclink_dc_in_v_status_overvoltage (dcin_overvoltage),
.lvmc_dclink_dc_in_v_status_undervoltage (dcin_undervoltage),
.lvmc_dclink_dc_in_v_status_chopper (),
.lvmc_dclink_dc_in_i_status_sync_dat (INPUT_CURRENT_MDAT),
.lvmc_dclink_dc_in_i_status_dc_link_enable (1'b1),
.lvmc_dclink_dc_in_i_status_overvoltage (dcin_overcurrent),
.lvmc_dclink_dc_in_i_status_undervoltage (),
.lvmc_dclink_dc_in_i_status_chopper (),
.lvmc_dclink_dc_link_i_status_sync_dat (DCBUS_CURRENT_MDAT),
.lvmc_dclink_dc_link_i_status_dc_link_enable (1'b1),
.lvmc_dclink_dc_link_i_status_overvoltage (dclink_overcurrent),
.lvmc_dclink_dc_link_i_status_undervoltage (),
.lvmc_dclink_dc_link_i_status_chopper (),
// SPI control bus for inverter gate drivers
.gate_drive_spi_MISO (DRV_SOMI),
.gate_drive_spi_MOSI (DRV_SIMO),
.gate_drive_spi_SCLK (DRV_SCLK),
.gate_drive_spi_SS_n (gate_drive_spi_ss_n),
.encoder_select_export (encoder_select),
.sync_in_export (1'b0),
// Axis 0
.drive0_adc_sync_dat_u (DRV0_U_CURRENT_MDAT),
.drive0_adc_sync_dat_v (DRV0_V_CURRENT_MDAT),
.drive0_adc_sync_dat_w (DRV0_W_CURRENT_MDAT),
.drive0_adc_overcurrent (Overcurrent0),
.drive0_adc_pow_sync_dat_u (DRV0_U_VOLTS_MDAT),
.drive0_adc_pow_sync_dat_v (DRV0_V_VOLTS_MDAT),
.drive0_adc_pow_sync_dat_w (DRV0_W_VOLTS_MDAT),
.drive0_adc_pow_overcurrent (),
.drive0_sm_overcurrent (Overcurrent0),
.drive0_sm_overvoltage (1'b0),
.drive0_sm_undervoltage (1'b0),
.drive0_sm_chopper (1'b0),
.drive0_sm_dc_link_clk_err (1'b0),
.drive0_sm_igbt_err (~DRV0_FAULTn),
.drive0_sm_error_out (),
.drive0_sm_overcurrent_latch (oc_latch_led0),
.drive0_sm_overvoltage_latch (ov_latch_led0),
.drive0_sm_undervoltage_latch (),
.drive0_sm_dc_link_clk_err_latch (),
.drive0_sm_igbt_err_latch (),
.drive0_sm_chopper_latch (),
.drive0_pwm_encoder_strobe_n (enc_stb0_n),
.drive0_pwm_u_h (HSMC_DRV0_PWM_UH),
.drive0_pwm_u_l (HSMC_DRV0_PWM_UL),
.drive0_pwm_v_h (HSMC_DRV0_PWM_VH),
.drive0_pwm_v_l (HSMC_DRV0_PWM_VL),
.drive0_pwm_w_h (HSMC_DRV0_PWM_WH),
.drive0_pwm_w_l (HSMC_DRV0_PWM_WL),
.drive0_qep_strobe (~enc_stb0_n),
.drive0_qep_QEP_A (DRV0_QR_A),
.drive0_qep_QEP_B (DRV0_QR_B),
.drive0_qep_QEP_I (DRV0_QR_Z),
.drive0_hall_pio_export ({DRV0_QHR_W, DRV0_QHR_V, DRV0_QHR_U}),
.drive0_rslvr_spi_ctrl_MISO (1'b0),
.drive0_rslvr_spi_ctrl_MOSI (DRV0_SER_TX_RSLVR),
.drive0_rslvr_spi_ctrl_SCLK (DRV0_SER_CLK_RSLVR_CTRL),
.drive0_rslvr_spi_ctrl_SS_n (DRV0_RESOLVER_SSCS),
.drive0_rslvr_spi_posn_MISO (DRV0_SER_RX),
.drive0_rslvr_spi_posn_MOSI (),
.drive0_rslvr_spi_posn_SCLK (DRV0_SER_CLK_RSLVR_POSN),
.drive0_rslvr_spi_posn_SS_n (DRV0_RESOLVER_SCSB),
.drive0_rslvr_pio_in_port ({1'b0, DRV0_RESOLVER_ERRHLD}),
.drive0_rslvr_pio_out_port (drive0_rslvr_pio_out),
// Axis 1
.drive1_adc_sync_dat_u (DRV1_U_CURRENT_MDAT),
.drive1_adc_sync_dat_v (DRV1_V_CURRENT_MDAT),
.drive1_adc_sync_dat_w (DRV1_W_CURRENT_MDAT),
.drive1_adc_overcurrent (Overcurrent1),
.drive1_adc_pow_sync_dat_u (DRV1_U_VOLTS_MDAT),
.drive1_adc_pow_sync_dat_v (DRV1_V_VOLTS_MDAT),
.drive1_adc_pow_sync_dat_w (DRV1_W_VOLTS_MDAT),
.drive1_adc_pow_overcurrent (),
.drive1_sm_overcurrent (Overcurrent1),
.drive1_sm_overvoltage (1'b0),
.drive1_sm_undervoltage (1'b0),
.drive1_sm_chopper (1'b0),
.drive1_sm_dc_link_clk_err (1'b0),
.drive1_sm_igbt_err (~DRV1_FAULTn),
.drive1_sm_error_out (),
.drive1_sm_overcurrent_latch (oc_latch_led1),
.drive1_sm_overvoltage_latch (ov_latch_led1),
.drive1_sm_undervoltage_latch (),
.drive1_sm_dc_link_clk_err_latch (),
.drive1_sm_igbt_err_latch (),
.drive1_sm_chopper_latch (),
.drive1_pwm_encoder_strobe_n (enc_stb1_n),
.drive1_pwm_u_h (HSMC_DRV1_PWM_UH),
.drive1_pwm_u_l (HSMC_DRV1_PWM_UL),
.drive1_pwm_v_h (HSMC_DRV1_PWM_VH),
.drive1_pwm_v_l (HSMC_DRV1_PWM_VL),
.drive1_pwm_w_h (HSMC_DRV1_PWM_WH),
.drive1_pwm_w_l (HSMC_DRV1_PWM_WL),
.drive1_qep_strobe (~enc_stb1_n),
.drive1_qep_QEP_A (DRV1_QR_A),
.drive1_qep_QEP_B (DRV1_QR_B),
.drive1_qep_QEP_I (DRV1_QR_Z),
.drive1_hall_pio_export ({DRV1_QHR_W, DRV1_QHR_V, DRV1_QHR_U}),
.drive1_rslvr_spi_ctrl_MISO (1'b0),
.drive1_rslvr_spi_ctrl_MOSI (DRV1_SER_TX_RSLVR),
.drive1_rslvr_spi_ctrl_SCLK (DRV1_SER_CLK_RSLVR_CTRL),
.drive1_rslvr_spi_ctrl_SS_n (DRV1_RESOLVER_SSCS),
.drive1_rslvr_spi_posn_MISO (DRV1_SER_RX),
.drive1_rslvr_spi_posn_MOSI (),
.drive1_rslvr_spi_posn_SCLK (DRV1_SER_CLK_RSLVR_POSN),
.drive1_rslvr_spi_posn_SS_n (DRV1_RESOLVER_SCSB),
.drive1_rslvr_pio_in_port ({1'b0, DRV1_RESOLVER_ERRHLD}),
.drive1_rslvr_pio_out_port (drive1_rslvr_pio_out),
// DDR3 interface FPGA
.ddr3_fpga_mem_a (mem_a),
.ddr3_fpga_mem_ba (mem_ba),
.ddr3_fpga_mem_ck (mem_ck),
.ddr3_fpga_mem_ck_n (mem_ck_n),
.ddr3_fpga_mem_cke (mem_cke),
.ddr3_fpga_mem_cs_n (mem_cs_n),
.ddr3_fpga_mem_dm (mem_dm),
.ddr3_fpga_mem_ras_n (mem_ras_n),
.ddr3_fpga_mem_cas_n (mem_cas_n),
.ddr3_fpga_mem_we_n (mem_we_n),
.ddr3_fpga_mem_reset_n (mem_reset_n),
.ddr3_fpga_mem_dq (mem_dq),
.ddr3_fpga_mem_dqs (mem_dqs),
.ddr3_fpga_mem_dqs_n (mem_dqs_n),
.ddr3_fpga_mem_odt (mem_odt),
.ddr3_fpga_status_local_init_done (),
.ddr3_fpga_status_local_cal_success (),
.ddr3_fpga_status_local_cal_fail (),
.fpga_mem_oct_rzqin (mem_oct_rzqin),
//TSN sub system
//HPS io
.hps_io_hps_io_emac1_inst_TX_CLK (enet_hps_gtx_clk),
.hps_io_hps_io_emac1_inst_TXD0 (enet_hps_txd[0]),
.hps_io_hps_io_emac1_inst_TXD1 (enet_hps_txd[1]),
.hps_io_hps_io_emac1_inst_TXD2 (enet_hps_txd[2]),
.hps_io_hps_io_emac1_inst_TXD3 (enet_hps_txd[3]),
.hps_io_hps_io_emac1_inst_MDIO (enet_hps_mdio),
.hps_io_hps_io_emac1_inst_MDC (enet_hps_mdc),
.hps_io_hps_io_emac1_inst_RX_CTL (enet_hps_rx_dv),
.hps_io_hps_io_emac1_inst_TX_CTL (enet_hps_tx_en),
.hps_io_hps_io_emac1_inst_RX_CLK (enet_hps_rx_clk),
.hps_io_hps_io_emac1_inst_RXD0 (enet_hps_rxd[0]),
.hps_io_hps_io_emac1_inst_RXD1 (enet_hps_rxd[1]),
.hps_io_hps_io_emac1_inst_RXD2 (enet_hps_rxd[2]),
.hps_io_hps_io_emac1_inst_RXD3 (enet_hps_rxd[3]),
.hps_io_hps_io_sdio_inst_CMD (sd_cmd),
.hps_io_hps_io_sdio_inst_CLK (sd_clk),
.hps_io_hps_io_sdio_inst_D0 (sd_dat[0]),
.hps_io_hps_io_sdio_inst_D1 (sd_dat[1]),
.hps_io_hps_io_sdio_inst_D2 (sd_dat[2]),
.hps_io_hps_io_sdio_inst_D3 (sd_dat[3]),
.hps_io_hps_io_uart0_inst_RX (uart_rx),
.hps_io_hps_io_uart0_inst_TX (uart_tx),
.hps_io_hps_io_i2c0_inst_SDA (i2c_sda_hps),
.hps_io_hps_io_i2c0_inst_SCL (i2c_scl_hps),
//HPS memory
.memory_mem_a (ddr3_hps_a),
.memory_mem_ba (ddr3_hps_ba),
.memory_mem_ck (ddr3_hps_ck),
.memory_mem_ck_n (ddr3_hps_ck_n),
.memory_mem_cke (ddr3_hps_cke),
.memory_mem_cs_n (ddr3_hps_cs_n),
.memory_mem_ras_n (ddr3_hps_ras_n),
.memory_mem_cas_n (ddr3_hps_cas_n),
.memory_mem_we_n (ddr3_hps_we_n),
.memory_mem_reset_n (ddr3_hps_reset_n),
.memory_mem_dq (ddr3_hps_dq),
.memory_mem_dqs (ddr3_hps_dqs),
.memory_mem_dqs_n (ddr3_hps_dqs_n),
.memory_mem_odt (ddr3_hps_odt),
.memory_mem_dm (ddr3_hps_dm),
.memory_oct_rzqin (ddr3_hps_oct_rzqin),
//HPS TSN
.eth_mdio_tristate_0_mdio_mdc (eth_mdio_tristate_0_mdio_mdc),
.eth_mdio_tristate_0_mdio_mdio (eth_mdio_tristate_0_mdio_mdio),
.de_ip_solution_scv_0_pps_pps (pps),
.pio_0_external_connection_export (enet_dual_resetn),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_rx_clk (deip_0_gmii_to_mii_0_mii_rx_clk),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_rx_dv (deip_0_gmii_to_mii_0_mii_rx_dv),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_rxd (deip_0_gmii_to_mii_0_mii_rxd),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_rx_er (deip_0_gmii_to_mii_0_mii_rx_er),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_tx_clk (deip_0_gmii_to_mii_0_mii_tx_clk),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_tx_en (deip_0_gmii_to_mii_0_mii_tx_en_i),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_txd (deip_0_gmii_to_mii_0_mii_txd_i),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_tx_er (),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_crs (1'b0),
.de_ip_solution_scv_0_gmii_to_mii_0_mii_mii_col (1'b0),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_rx_clk (deip_0_gmii_to_mii_1_mii_rx_clk),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_rx_dv (deip_0_gmii_to_mii_1_mii_rx_dv),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_rxd (deip_0_gmii_to_mii_1_mii_rxd),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_rx_er (deip_0_gmii_to_mii_1_mii_rx_er),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_tx_clk (deip_0_gmii_to_mii_1_mii_tx_clk),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_tx_en (deip_0_gmii_to_mii_1_mii_tx_en_i),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_txd (deip_0_gmii_to_mii_1_mii_txd_i),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_tx_er (),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_crs (1'b0),
.de_ip_solution_scv_0_gmii_to_mii_1_mii_mii_col (1'b0)
);
endmodule