AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
Document Table of Contents

1.4. Design Flow for the TSN Drive-on-Chip Design Example

Intel does not supply source files, images, configuration files but does describe how to create them.
  1. Download both the Drive-on-Chip application and TTTech TSN IP onto the FPGA.
  2. Store them in the EPCQ memory of the Cyclone V SoC Development board using a .jic format file. The .jic file is a combination of the .sof output file (product of the Intel Quartus Compilation) and an .hex file (product of the Drive-on-Chip software compilation). The Drive-on-Chip design runs on the Nios II soft processor using the µCOSII (Real Time OS) framework.
  3. Program the TTTech TSN IP into the FPGA and it uses the HPS within the Cyclone V SoC to run Linux and manage the TSN system. The Intel Quartus Prime compilation for the project produces handoff files. These are input of BSP editor (part of SoC EDS) to create an HPS preloader.
  4. Use this preloader image to create an SD card image for the HPS to boot-up Linux.
  5. Build an SD card image for the development board using the YOCTO project. TTTech customized the flow to meet its IP requirements and tools. YOCTO is a method for building customized embedded Linux distributions.
  6. Describe, by using recipes, the components of your system and produce a bootable SD card image (or files) as the product of the build. For more information, refer to the YOCTO PROJECT website. A Linux machine launches the YOCTO build, as it cannot build on a mounted NFS volume.
  7. Patch the YOCTO build to adapt it to Cyclone V SoC Development board.
  8. Use the design as a base to integrate the TSN drive-on-chip hardware in Intel Quartus Prime. For Smart Factory solutions, the Linux distribution of the TTTech IP reference design (5.4.40) can be patched with Linux RT-patch 5.4.40-rt24 HPS runs Linux, necessary daemons, TTTech TSN drivers, and any other high-level application you program.