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1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example
2.2. Software Requirements for the TSN for Drive-on-Chip Design Example
2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example
2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example
2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example
2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example
2.7. Configuring the TSN IP
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example
3.2. Modifying the Drive-On-Chip Qsys System
3.3. Adding the TTTech TSN IP to the Qsys system
3.4. Connecting the TSN and Drive-on-Chip Subsystems
3.5. Compiling the Quartus Prime Design and Top-Level Module
3.6. Generating the Preloader
3.7. Generating a .jic file
3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools
3.9. Launching a YOCTO Build
3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example
3.11. Changing MAC Addresses
3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
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1.3. Messages from the TSN Drive-on-Chip Design Example
Cyclone V SoC Development board
You can run the OPC UA PubSub application on the Cyclone V SoC Development board. You can compile the design in DS-5 environment or standalone using the Arm compiler (cross-compilation). The incoming messages can include motor commands and motor parameters. Published messages from the SoC can include measurements and parameters from the motor. Besides OPC UA PubSub, the SoC can support other applications such as OPC UA Client-Server.
TSN scheduled messages
You can implement IEEE 802.1Qbv scheduling by either:
- Using VLANs for stream differentiation and IEEE 802.1Qbv configuration in the command line using sgs and tsntool (refer to TTTech TSN IP Reference Design for DE-IP-SCV user manual).
- Using TTTech SlateXNS: a browser-based tool used to create schedules and deploy configurations to switches using Netconf over TLS
Motor commands and recorded data over TSN
You can control, within the network, certain motor parameters: rotational speed, position commands, speed limits and other parameters to adjust the control loops. The OPC UA Publisher (or client/server) controller sends these messages to the Cyclone V SoC Development board by overriding the corresponding attribute. Also, you can return parameters and performance values to the network by programming an OPC UA Publisher in the SoC and giving these message priority and schedule.