AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
Document Table of Contents
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1. About the Time-Sensitive Networking for Drive-on-Chip Design Example

This design ports the TTTech TSN IP functionality to the Cyclone V SoC Development board. This design shows how the motor control and time-sensitive networking (TSN) can work together in a flexible and efficient FPGA implementation.

The design integrates:

  • The Drive-On-Chip Design Example for Intel MAX 10 devices
  • The TTTech TSN IP

The TTTech TSN IP includes all the tools (DE-PTP, tsntool, deptp_tool, Netconf, YANG, SSH) necessary to set up an Ethernet connection over TSN using the device. You can run a high-level communication protocol such OPC UA (client-server or PubSub) over TSN.

The design allows you to learn about drive-on-chip applications and TSN functionality. The design incorporates TSN and OPC UA and the versatility of motor control embedded in an Intel FPGA device.

Industry 4.0 industrial networking standards OPC UA PubSub and TSN are possible on a local network with multiple devices. Industry 4.0 allow you to migrate towards TSN to consolidate communication in a single network that is efficient, secure, and reliable. You can add every node in the factory from industrial PCs to sensors to the TSN network including embedded motor control. In industry 4.0, TSN is becoming more relevant with communication protocols such as OPC UA PubSub. FPGAs allow you to introduce new hardware and SoC products into the manufacturing environment.

You build the FPGA bitstream and the SD card image for the TTTech TSN IP and the Intel Drive-On-Chip for Intel MAX 10 design.

Intel integrated the TSN IP into the design using TTTech DE-EVAL reference design.

Figure 1. TSN Drive-on-Chip Design Block Diagram