AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

7. TSN Configuration Example

The TSN configuration relates to the application that the Cyclone V SoC Development board runs. For more details about PTP, Qbv, TSN, VLAN.; refer to the TTTech TSN IP Reference Design for DE-IP-SCV user manual

The OPC UA Publisher is using the multicast MAC address 01-00-5E-00-00-02 with the VLAN tag 3 and PCP (Priority Code Point) 7. Therefore, configure the VLAN as: 

>> ssh root@192.168.1.20 (default IP address Development board)
>> ip link add link sw0ep name myvlan type vlan id 3 (add VLAN id 3) 
>> ip link set dev myvlan up (set the VLAN up) 
>> bridge vlan add vid 3 dev sw0p1 (add VLAN to internal port) 
>> bridge vlan add vid 3 dev sw0p2 (add VLAN to external port 1) 
>> bridge vlan add vid 3 dev sw0p3 (optional if second port is used)

If the Publisher (outgoing traffic) requires TSN configuration, add a Qbv schedule. For example:

>> tsntool st wrcl sw0p2 /home/root/scripts/qbv.conf(write the schedule, port 1) 
>> tsntool st wrcl sw0p3 /home/root/scripts/qbv.conf(write the schedule, port 2) 
>> tsntool st rdacl sw0p2 /dev/stdout(to read) 
>> tsntool st configure 0.0 1/1000 10000 sw0p2 (configure the schedule 1ms interval) 
>> tsntool st configure 0.0 1/1000 10000 sw0p3

The parameters can vary according to your specification. Also, qbv.conf is a file specifying the schedule. For example, a 1 ms schedule: 

 
sgs 400000 0x80 (high priority traffic) 
sgs 100000 0x7E (other traffic)
sgs 400000 0x80 
sgs 100000 0x7f

To check the status of the precision time protocol (PTP) clock synchronization across devices that are TSN capable use DEPTP_TOOL provided by TTTech : 

 >> deptp_tool –get-current-dataset
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