1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
3.6. Generating the Preloader
The preloader is an essential component for the TSN drive-on-chip design HPS to boot-up. The Intel Quartus compilation generates a directory hps_isw_handoff. Every time you modify the Qsys system or the Intel Quartus Prime project, you must generate a new preloader and include it in the SD card image for the HPS.
- Open the SoC EDS Command Shell and navigate to the directory /<project_location>/software_hps/spl_bsp (or create it within the project files) and run the bsp-editor.
- Click File > New HPS BSP…
- Set the Preloader settings directory: to <project_location>/hps_isw_handoff/DOC_TANDEM_CVSX_NIOS_TSN_QSYS_hps_0
- Turn off Use default locations and change the target directory to <project location>/software_hps/spl_bsp, click OK.
- In the BSP Editor settings window, turn on FAT support, turn off the watchdog, and turn on SDRAM_SCRUBBING
Figure 27. BSP editor to generate preloader
- Press Generate and close the window
- In the SoC EDS Command Shell navigate to <project_location>/software_hps/spl_bsp.
- Do a make clean and then a make all.
If you see any error regarding tar.gz file decompression, use /usr/bin/make.exe to compile.
The file preloader-mkpimage.bin generates, which integrates into the SD card image for the HPS booting process.