AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
Document Table of Contents

1.1. Features of TSN for Drive-on-Chip Design Example

The Cyclone V SoC Development board offers

  • A two-port switched endpoint
  • TTTech TSN IP flashed onto Cyclone V SoC
  • Drive on Chip design running on Nios II soft processor in the Cyclone V SoC (µCOS II)
  • TTTech TSN IP in the FPGA.
  • SD card boot uses TTTech TSN IP but does not configure the FPGA.
  • HPS (Arm processor) that runs Linux and TTTech TSN drivers.
  • On-board EPCQ memory that programs the FPGA and stores the Nios II drive-on-chip application software.

The Tandem Motion-Power 48 V Board offers:

  • Dual-axis motor control
  • A visual TSN and OPC UA endpoint for demonstrations