3.5. Compiling the Quartus Prime Design and Top-Level Module
- Add the license to the Quartus license files ( Tools > License Setup).
- Compile the design to obtain the output .sof file.
Usually you configure FPGA with the .sof files. However, for this design, the FPGA image is stored in the EPCQ flash memory with the Nios II program.
Refer to Example .qsf for Pin Assignments and Attributes for the pin assignments for the TSN drive-on-chip design targeting the Cyclone V SoC Development Board . Apart from the pin assignment, some pins include attributes that are necessary for the correct behavior of the TSN IP and drive-on-chip design.