AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
Document Table of Contents
Give Feedback

3.5. Compiling the Quartus Prime Design and Top-Level Module

The TSN drive-on-chip Qsys project is wrapped into a top-level Verilog HDL file that instantiates and exposes the inputs and outputs of the Qsys module DOC_TANDEM_CVSX_NIOS_TSN_QSYS. To compile the project, you must have a TTTech TSN IP License.
  1. Add the license to the Quartus license files ( Tools > License Setup).
  2. Compile the design to obtain the output .sof file.
    Usually you configure FPGA with the .sof files. However, for this design, the FPGA image is stored in the EPCQ flash memory with the Nios II program.

    Refer to Example .qsf for Pin Assignments and Attributes for the pin assignments for the TSN drive-on-chip design targeting the Cyclone V SoC Development Board . Apart from the pin assignment, some pins include attributes that are necessary for the correct behavior of the TSN IP and drive-on-chip design.