AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

Download PDF
ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

3.9. Launching a YOCTO Build

The SD card image for the HPS in the TSN drive-on-chip design is entirely based on the framework provided by TTTech. To build all the components into an SD card for HPS booting, you need a new YOCTO build to migrate from the DE-EVAL-BOARD (Reference Design) to the Cyclone V SoC Development board.

You must run these steps on a Linux Machine.

  1. Get the TTTech IP .zip file and decompress it.
  2. Navigate to de-eval-board/build and decompress de-evaluation-board-src.tar.gz, which contains all the files for the YOCTO build.
  3. Manually include the preloader and create the SD card image using individual components.
The patch includes the following changes:
  • de-eval-board/socfpga.c: change the offset to access the EEPROM that stores the MAC addresses in the Cyclone V SoC Development Board
  • sdcard-image_1.0.0.bb: add additional software to the build including the rt-tests.
  • ttt-ip-init.sh: TTTech IP initialization script. Change the function to access the MAC addresses for the interfaces from EEPROM and set the PHY delays for the interfaces.
  • de-eval-board/ interfaces: change the IP address and remove additional switch ports (only two out of four are used)
  • /machine/de-eval-board.conf: add tar.gz as root file system output extension, to generate the root file system for the SD card image.
  • /de-eval-board/u-boot.script: disable programming the FPGA fabric from the SD card. The image for the FPGA comes from the EPCQ memory in this description of the solution.
  • socfpga_cyclone5_de-eval-board_default.dts: change the register address for the EEPROM refer to Script to read and change MAC addresses from Cyclone V SoC EEPROM.
  • Linux-tttech-industrial_5.4.bb: add the RT patch (optional).
Level Two Title