AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

ID 683707
Date 10/30/2021
Document Table of Contents

3.9. Launching a YOCTO Build

The SD card image for the HPS in the TSN drive-on-chip design is entirely based on the framework provided by TTTech. To build all the components into an SD card for HPS booting, you need a new YOCTO build to migrate from the DE-EVAL-BOARD (Reference Design) to the Cyclone V SoC Development board.

You must run these steps on a Linux Machine.

  1. Get the TTTech IP .zip file and decompress it.
  2. Navigate to de-eval-board/build and decompress de-evaluation-board-src.tar.gz, which contains all the files for the YOCTO build.
  3. Manually include the preloader and create the SD card image using individual components.
The patch includes the following changes:
  • de-eval-board/socfpga.c: change the offset to access the EEPROM that stores the MAC addresses in the Cyclone V SoC Development Board
  • add additional software to the build including the rt-tests.
  • TTTech IP initialization script. Change the function to access the MAC addresses for the interfaces from EEPROM and set the PHY delays for the interfaces.
  • de-eval-board/ interfaces: change the IP address and remove additional switch ports (only two out of four are used)
  • /machine/de-eval-board.conf: add tar.gz as root file system output extension, to generate the root file system for the SD card image.
  • /de-eval-board/u-boot.script: disable programming the FPGA fabric from the SD card. The image for the FPGA comes from the EPCQ memory in this description of the solution.
  • socfpga_cyclone5_de-eval-board_default.dts: change the register address for the EEPROM refer to Script to read and change MAC addresses from Cyclone V SoC EEPROM.
  • add the RT patch (optional).