3.3. Adding the TTTech TSN IP to the Qsys system
You build the TSN system within the TSN drive-on-chip design based on TTTech TSN IP.
- Copy the directory ip-sol-scv-release-2.3.0-30_03_2021\de_ip_solution_scv to <Quartus_Project>/ip and ip-sol-scv-release-2.3.0-30_03_2021\de-eval-board\fpga\misc_ip to <Quartus_Project>/ip.
- In Qsys, click IP search paths.
and add the newly copied directories to the Qsys automatically adds the TTTech IP to the IP catalog in the left upper corner of Qsys.Figure 15. TTTech TSN IP in IP Catalog
- Navigate to ip-sol-scv-release-2.3.0-30_03_2021\de-eval-board\fpga and open de-eval_scv.qar with Intel Quartus Prime.
The design opens including a Qsys system. The blocks in this design are identical to the ones in the TTTech Reference Design.
- In the Qsys system add the following functional blocks and connect them in the same way as the TTTech Reference Design.
Table 5. TSN subsystem blocks, addresses, and interrupts Module Name Description Port Address Base and Interrupt number hps_0 Arria V/ Cyclone V Hard Processor System f2h_sdram0_data 0x0000_0000 f2h_sdram1_data 0x0000_0000 f2h_ir10 IRQ 0 mm_bridge_0 Avalon-MM PipelineBridge s0 0x0000_0000 sys_qsys_0 System ID Peripheral control_slave 0x0001_0000 System ID 0x1c7e0004 rev_id_0 Internal Revision ID s 0x0004_0500 QSYS_SVM_ID 165499264 pio_0 PIO (Parallel I/O) s1 0x000f_0f00 eth_mdio_tristate_0 Altera’s Ethernet MDIO master with tristate logic csr 0x000f_0200 de_ip_solution_csv_0 DE-IP Solution SCV s_deip 0x0200_0000 irq0-ir115 0-15
- Connect the TSN blocks with a 100 MHz clock from the drive-on-chip subsystem.
- Add another Altera PLL block with the same 50 MHz reference clock as input (the same reference clock as the PLL for the drive-on-chip subsystem)
This additional 125 MHz clock is for the TSN IP m_dma_0_clk port.
- Configure the TSN IP with these parameters:
- Generics: BUS_CDC 0, FES_PORT_HIGH 2, BUFFER_SIZE 0, SCHEDULED_PORTS 31, PREEMPTABLE_PORTS 30, FRER_PORTS 31
- Options: LED_ACTIVE 0, Enable link LED interface (turn off)
- Adapters: Port 0 interface type DMA, Port 1 Interface Type MII, Port 2 Interface Type MII.
- Keep the multiple PIO blocks in the TTTech TSN IP Reference Design Qsys System and change the equivalent to pio_phy_reset (pio_0).
Keep the other PIO modules such as pio_led_debug, pio_pps_debug_out and pio_pps_debug_in.
- Configure the HPS module, even though the HPS and the secondary modules are connected in the same way as the TTTech TSN IP Reference Design Qsys system.
The HPS within the Cyclone V SoC Development board is connected to a different DDR3 memory than the TTTech Reference Board.Figure 16. HPS SettingsFigure 17. HPS SettingsFigure 18. HPS SettingsFigure 19. HPS SettingsFigure 20. HPS SettingsFigure 21. HPS SettingsFigure 22. HPS SettingsFigure 23. HPS SettingsFigure 24. HPS Settings
Both the drive-on-chip and TSN subsystems now work separately.