Intel® Cyclone® 10 GX Device Design Guidelines

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ID 683703
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Design Guidelines
Intel® Cyclone® 10 GX Device Design Guidelines x
System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering PLLs and Clock Routing Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Quartus Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
Configuration Features x
Data Compression Design Security Using Configuration Bitstream Encryption Remote System Upgrades SEU Mitigation and CRC Error Checks
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Quartus Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL and Transceiver Board Design Guidelines
Configuration Pin Connections x
DCLK and TCK Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
Board-Related Quartus Prime Settings x
Device-Wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Block I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable I/O Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Cyclone® 10 GX I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles Register Power-Up Levels and Control Signals Planning for Hierarchical and Team-Based Design
Reconfiguration x
Dynamic Reconfiguration
Planning for Hierarchical and Team-Based Design x
Planning Design Partitions Planning in Bottom-Up and Team-Based Flows Creating a Design Floorplan
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Quartus Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Formal Verification Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Quartus Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Quartus Prime Power Optimization Techniques x
Power Optimization Advisor
Appendix: Cyclone® 10 GX Transceiver Design Guidelines x
Transceiver PHY Architecture Overview Transceiver Bank Architecture PHY Layer Transceiver Components Transceiver Phase-Locked Loops Clock Generation Block (CGB) Calibration Transceiver Design Flow
PHY Layer Transceiver Components x
The GX Transceiver Channel
Transceiver Phase-Locked Loops x
Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Channel PLL (CMU/CDR PLL)
Intel® Cyclone® 10 GX Device Design Guidelines

Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes six transceiver channels in all devices except for the devices with 10 transceiver channels.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

Figure 3. Six-Channel GX Transceiver Bank Architecture

The transceiver channels perform all the required PHY layer functions between the FPGA fabric and the physical medium. The high speed clock required by the transceiver channels is generated by the transceiver PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.

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