Embedded Design Handbook

ID 683689
Date 8/28/2023
Public
Document Table of Contents

6.3.1.4.1. Signal Probe Signal Probe

The Signal Probe incremental routing feature allows you to route signals to output pins of the FPGA without affecting the existing fit of a design to a significant degree. You can use Signal Probe to investigate internal device signals without rewriting your HDL code to pass them up through multiple layers of the design hierarchy to a pin. Creating such revisions manually is time-consuming and error-prone.

Intel recommends Signal Probe when there are enough pins to route internal signals out of the FPGA for verification. If FPGA pins are not available, you have the following three alternatives:

  • Reduce the number of pins used by the design to make more pins available to Signal Probe
  • Use the Signal Tap II embedded logic analyzer
  • Use the Logic Analyzer Interface

Revising your design to increase the number of pins available for verification purposes requires design changes and can impact the design schedule. Using the Signal Tap II embedded logic analyzer is a viable solution if you do not require continuous sampling at a high rate. The Signal Tap II embedded logic analyzer does not require any additional pins to be routed; however, you must have enough unallocated logic and memory resources in your design to incorporate it. If neither of these approaches is viable, you can use the logic analyzer interface.

To learn more about Signal Probe, refer to the Quick Design Debugging Using Signal Probe chapter in the Intel® Quartus® Prime Handbook Volume 3: Verification.