Embedded Design Handbook

ID 683689
Date 8/28/2023
Public
Document Table of Contents

7.1.2.3.1. Low-Speed State Machines

Low-speed state machines are typically used to control peripherals. The Nios II/e processor pictured in Figure 275 could implement a low speed state machine to control the peripherals.

Even though the Nios® II/e core does not include a data cache, Intel recommends that the software accessing the peripherals use data cache bypassing. Doing so avoids potential cache coherency issues if the software is ever run on a Nios® II/f core that includes a data cache.

For information about data cache bypass methods, refer to the Processor Architecture chapter of the Nios® II Gen2 Processor Reference Handbook.

State machines implemented in Platform Designer require the following components:

  • A Nios® II processor
  • Program and data memory
  • Stimuli interfaces
  • Output interfaces

The building blocks you use to construct a state machine in Platform Designer are no different than those you would use if you were creating a state machine manually. One noticeable difference in the Platform Designer environment is accessing the interfaces from the Nios® II processor. The Nios® II processor uses an Avalon® -MM master port to access peripherals. Instead of accessing the interfaces using signals, you communicate via memory-mapped interfaces. Memory-mapped interfaces simplify the design of large state machines because managing memory is much simpler than creating numerous directly connected interfaces.

For more information about the Avalon® -MM interface, refer to the Avalon® Interface Specifications.