Visible to Intel only — GUID: iga1464289942329
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Visible to Intel only — GUID: iga1464289942329
Ixiasoft
7.5.5.2. Modify the Example Design to Include Tightly Coupled Memories
First, create a new hardware reference design with tightly coupled memories that is based on the Nios® II Ethernet standard design example. To create this modified reference design, perform the following steps:
- Navigate to the Nios® II Ethernet Standard Design Example web page and locate the Nios® II Ethernet Standard design example .zip file that corresponds to your board.
- Extract the files from the downloaded .zip file and copy the niosii_ethernet_standard_ <board> directory to a new directory named standard_tcm.
- In the Windows Start menu, choose Programs > Intel FPGA > Intel® Quartus® Prime <version> to run the Intel® Quartus® Prime software.
- On the File menu, click Open Project and browse to the standard_tcm\niosii_ethernet_standard_ <board> .qpf project file. Click Open.
- On the Tools menu, click Platform Designer . When prompted, select eth_std_main_system.qsys and click Open to open the Platform Designer design.
- Double-click the cpu component in the list of available components on the System Contents tab to open the Nios® II processor configuration wizard.
- Ensure that Nios® II/f is selected on the Core Nios® II tab.
- Click the Caches and Memory Interfaces tab.
- Select the number of instruction master ports in the drop-down list next to Number of tightly coupled instruction master port(s). In this example, select 1 port.
- Change the Instruction cache to 4 KB.
- Select the number of instruction master ports in the drop-down list next to Number of tightly coupled data master port(s). In this example, select 1 port.
- Change the Data cache to 2 KB and Data Cache Line Size to 4 Bytes.
- Click Finish to close the Nios® II processor configuration wizard.
Two new master ports now appear under the cpu component called tightly_coupled_instruction_master_0 and tightly_coupled_data_master_0. These master ports are not yet connected to the slave ports.