Embedded Design Handbook

ID 683689
Date 8/28/2023
Public
Document Table of Contents

7.1.2.1. Creating Multicore Designs

Multicore designs combine multiple processor cores in a single FPGA to create a higher performance computing system. Typically, the processors in a multicore design can communicate with each other. Designs including the Nios® II processor can implement inter-processor communication, or the processors can operate autonomously.

When a design includes more than one processor you must partition the algorithm carefully to make efficient use of all of the processors. The following example includes a Nios® II-based system that performs video over IP, using a network interface to supply data to a discrete DSP processor. The original design overutilizes the Nios® II processor. The system performs the following steps to transfer data from the network to the DSP processor:

  1. The network interface signals when a full data packet has been received.
  2. The Nios® II processor uses a DMA engine to transfer the packet to a dual-port on-chip memory buffer.
  3. The Nios® II processor processes the packet in the on-chip memory buffer.
  4. The Nios® II processor uses the DMA engine to transfer the video data to the DSP processor.

In the original design, the Nios® II processor is also responsible for communications with the following peripherals that include Avalon® -MM slave ports:

  • Hardware debug interface
  • User interface
  • Power management
  • Remote control receiver
Figure 275. Over-Utilized Video System

Adding a second Nios® II processor to the system, allows the workload to be divided so that one processor handles the network functionality and the other the control interfaces.

Because the revised design has two processors, you must create two software projects; however, each of these software projects handles fewer tasks and is simpler to create and maintain. You must also create a mechanism for inter-processor communication. The inter-processor communication in this system is relatively simple and is justified by the system performance increase.

For more information about designing hardware and software for inter-processor communication, refer to the Creating Multiprocessor Nios® II Systems Tutorial and the Peripherals section of the Embedded Peripherals IP User Guide. Refer to the Nios® II Gen2 Processor Reference Handbook for complete information about this soft core processor. A Nios® II Multiprocessor Design Example is available on the Intel website.

Figure 276. High Performance Video System

In the figure above, the second Nios® II processor added to the system performs primarily low-level maintenance tasks; consequently, the Nios® II/e core is used. The Nios® II/e core implements only the most basic processor functionality in an effort to trade off performance for a small hardware footprint. This core is approximately one-third the size of the Nios® II/f core. To have uninterrupted Nios® II/f core, set memory arbiter to give low priority to the Nios® II/e core.

To learn more about the three Nios® II processor cores refer to the Nios® II Core Implementation Details chapter in the Nios® II Gen2 Processor Reference Handbook.