Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.4.1. TX Reset and Initialization Sequence

The TX reset sequence for Serial Lite IV Intel® FPGA IP is as follows:
  1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, and reconfig_reset simultaneously to reset the custom PCS, MAC, and reconfiguration blocks. Release the custom PCS (tx_pcs_fec_phy_reset_n) and reconfiguration reset (reconfig_reset) after 200 ns to ensure the blocks are properly reset.
  2. The IP then asserts the phy_tx_lanes_stable, tx_pll_locked, and phy_ehip_ready signals after the custom PCS reset is released, to indicate the TX PHY is ready for transmission.
  3. The tx_core_rst_n signal deasserts after phy_ehip_ready signal goes high.
  4. The IP starts transmitting IDLE characters on the MII interface once the MAC is out of reset. There is no requirement for TX lane alignment and skewing because all lanes use the same clock.
  5. While transmitting IDLE characters, the MAC asserts the tx_link_up signal.
  6. The MAC then starts transmitting ALIGN paired with START/END or END/START CWs at a fixed interval to initiate the lane alignment process of the connected receiver.
Figure 23. TX Reset and Initialization Timing Diagram

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