Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

6.2. Reset Signals

Table 23.  Reset Signals
Name Width Direction Clock Domain Description
tx_core_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the Serial Lite IV TX MAC.

rx_core_rst_n 1 Input Asynchronous Active-low reset signal.

Resets the Serial Lite IV RX MAC.

tx_pcs_fec_phy_reset_n 1 Input Asynchronous Active-low reset signal.

Resets the Serial Lite IV TX custom PCS.

rx_pcs_fec_phy_reset_n 1 Input Asynchronous Active-low reset signal.

Resets the Serial Lite IV RX custom PCS.

reconfig_reset
  • lane/2 (PAM4 mode)
  • lane/4 (NRZ mode)
Input reconfig_clk Active-high reset signal.

Resets the Avalon® memory-mapped interface reconfiguration block.

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