Serial Lite IV Intel® FPGA IP User Guide

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ID 683655
Date 12/01/2021
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4.4.1. Simulating and Verifying the Design

By default, the parameter editor generates simulator-specific scripts containing commands to compile, elaborate, and simulate Intel FPGA IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.

Table 19.   Intel FPGA IP Core Simulation Scripts

Simulator

File Directory

Script

ModelSim*

<variation name>_ sim/mentor

msim_setup.tcl 8

QuestaSim*
VCS*

<variation name>_ sim/synopsys/vcs

vcs_setup.sh

VCS* MX

<variation name>_ sim/synopsys/vcsmx

vcsmx_setup.sh

synopsys_sim.setup

Xcelium*

<variation name>_ sim/xcelium

xcelium_setup.sh
8 If you did not set up the EDA tool option— which enables you to start third-party EDA simulators from the Intel® Quartus® Prime software—run this script in the ModelSim* or QuestaSim* simulator Tcl console (not in the Intel® Quartus® Prime software Tcl console) to avoid any errors.

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