Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.2.4. RX Deskew

The RX deskew block detects the alignment markers for each lane and re-aligns the data before sending it to the RX CW removal block.

You can choose to let the IP core to align the data for each lane automatically when an alignment error occurs by setting the Enable Auto Alignment parameter in the IP parameter Editor. If you disable the automatic alignment feature, the IP core asserts the rx_error signal to indicate alignment error. You must assert the rx_link_reinit to initiate the lane alignment process when a lane alignment error occurs.

The RX deskew detects the alignment markers based on a state machine. The following diagram shows the states in the RX deskew block.
Figure 17. RX Deskew Lane Alignment State Machine with Auto Alignment Enabled Flow Chart
Figure 18. RX Deskew Lane Alignment State Machine with Auto Alignment Disabled Flow Chart
  1. The alignment process starts with the IDLE state. The block moves to WAIT state when all PCS lanes are ready and rx_link_reinit is deasserted.
  2. In WAIT state, the block checks all detected markers are asserted within the same cycle. If this condition is true, the block moves to the ALIGNED state.
  3. When the block is in the ALIGNED state, it indicates the lanes are aligned. In this state, the block continues to monitor lane alignment and check if all markers are present within the same cycle. If at least one marker is not present in the same cycle and the Enable Auto Alignment parameter is set, the block goes to the IDLE state to re-initialize the alignment process. If Enable Auto Alignment is not set and at least one marker is not present in the same cycle, the block goes to ERROR state and waits for the user logic to assert rx_link_reinit signal to initiate lane alignment process.
Figure 19. Lane Realignment with Enable Auto Alignment Enabled
Figure 20. Lane Realignment with Enable Auto Alignment Disabled

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