Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

6.1. Clock Signals

Table 22.  Clock Signals
Name Width Direction Description
tx_core_clkout 1 Output TX core clock for the TX custom PCS interface, TX MAC and user logics in the TX datapath.

This clock is generated from the custom PCS block.

rx_core_clkout 1 Output RX core clock for the RX custom PCS interface, RX deskew FIFO, RX MAC and user logics in the RX datapath.

This clock is generated from the custom PCS block.

xcvr_ref_clk 1 Input Transceiver reference clock.

The IP supports reference clocks provided from separate clock chips or oscillators with a tolerance of ±100 ppm clock variation between the different clock chips or oscillators.

Refer to Parameters for supported frequency range.

reconfig_clk 1 Input Input clock for transceiver reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.

xcvr_ref_clk_1 1 Input Transceiver reference clock used for preservation of unused transceiver channels.

This clock is only applicable in PAM4 mode when you turn on Preserve unused transceiver channels for PAM4 in the IP parameter editor. In NRZ mode, this clock is available by default.

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