3. Functional Description
Serial Lite IV Intel FPGA IP consists of MAC and custom PCS. The MAC communicates with the custom PCS through MII interfaces.
- PAM4—Provides 2, 4, 6, or 8 number of lanes for selection. A PCS block in PAM4 modulation mode contains four Ethernet channels. The IP always instantiates two PCS channels for each lane in PAM4 modulation mode.
- NRZ—Provides 1 to 16 number of lanes for selection. In this modulation mode, each PCS block supports up to a maximum of four Ethernet channels.
- Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
Figure 2. Basic Mode Data Transfer
- Full mode—This is the packet mode data transfer. In this mode, the IP sends a burst and a sync cycle at the start and the end of a packet as delimiters.
Figure 3. Full Mode Data Transfer
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