Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

2.2. Supported Features

The following table lists the features available in Serial Lite IV Intel® FPGA IP:
Table 4.   Serial Lite IV Intel® FPGA IP Features
Feature Description
Data Transfer
  • Supports up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link.
  • Supports up to 28 Gbps per lane with a maximum of 16 NRZ lanes.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • Supports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.
PCS
  • Uses hard IP logic that interfaces seamlessly to Intel® Stratix® 10 and Intel® Agilex™ E-tile transceivers for soft logic resource reduction.
  • Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is always enabled in this modulation mode.
  • Supports NRZ with optional RS-FEC modulation mode.
  • Supports 64b/66b encoding decoding.
Error Detection and Handling
  • Supports CRC error checking on TX and RX data paths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.
Interfaces
  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGA devices with low transfer latency.
  • Supports user-defined commands.

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