Serial Lite IV Intel® FPGA IP User Guide

Download PDF
ID 683655
Date 11/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

2.2. Supported Features

The following table lists the features available in Serial Lite IV Intel® FPGA IP:
Table 4.   Serial Lite IV Intel® FPGA IP Features
Feature Description
Data Transfer
  • Supports up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link.
  • Supports up to 28 Gbps per lane with a maximum of 16 NRZ lanes.
  • Supports continuous streaming (Basic) or packet (Full) modes.
  • Supports low overhead frame packets.
  • Supports byte granularity transfer for every burst size.
  • Supports user-initiated or automatic lane alignment.
  • Supports programmable alignment period.
PCS
  • Uses hard IP logic that interfaces seamlessly to Intel® Stratix® 10 and Intel® Agilex™ E-tile transceivers for soft logic resource reduction.
  • Supports PAM4 modulation mode for 100GBASE-KP4 specification. RS-FEC is always enabled in this modulation mode.
  • Supports NRZ with optional RS-FEC modulation mode.
  • Supports 64b/66b encoding decoding.
Error Detection and Handling
  • Supports CRC error checking on TX and RX data paths.
  • Supports RX link error checking.
  • Supports RX PCS error detection.
Interfaces
  • Supports only full duplex packet transfer with independent links.
  • Uses point-to-point interconnect to multiple FPGA devices with low transfer latency.
  • Supports user-defined commands.
Level Two Title