Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

2.5. Resource Utilization and Latency

The resources and latency for the Serial Lite IV Intel® FPGA IP were obtained from the Intel® Quartus® Prime Pro Edition software version 21.1.

Table 6.   Intel® Stratix® 10 Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Variant Number of Data Lanes Mode RS-FEC ALM Latency (TX core clock cycle)
28 Gbps NRZ 16 Basic Disabled 16,171 80
16 Full Disabled 16,724 82
16 Basic Enabled 15,383 239
16 Full Enabled 15,771 240
56 Gbps PAM4 8 Basic Enabled 11,197 154
8 Full Enabled 11,591 152
Table 7.   Intel® Agilex™ Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Variant Number of Data Lanes Mode RS-FEC ALM Latency (TX core clock cycle)
28 Gbps NRZ 16 Basic Disabled 16,480 80
16 Full Disabled 16,896 82
16 Basic Enabled 15,173 239
16 Full Enabled 15,534 240
56 Gbps PAM4 8 Basic Enabled 11,356 154
8 Full Enabled 11,448 152

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