Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.4. Reset and Link Initialization

The MAC, custom PCS, and reconfiguration blocks have different reset signals:
  • TX and RX MAC blocks use tx_core_rst_n and rx_core_rst_n reset signals.
  • TX and RX RS-FEC blocks use tx_pcs_fec_phy_reset_n and rx_pcs_fec_phy_reset_n reset signals.
  • Reconfiguration block uses the reconfig_reset reset signal.
Figure 22. Reset Architecture

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