Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.1.2. Control Word (CW) Insertion

The Serial Lite IV Intel® FPGA IP constructs CWs based on the input signals from the user logic. The CWs indicate packet delimiters, transmission status information or user data to the PCS block and they are derived from XGMII control codes.

The following table shows the description of the supported CWs:
Table 9.  Description of Supported CWs
CW Number of Words (1 word = 64 bits) In-band Description
START 1 Yes Start of data delimiter.
END 1 Yes End of data delimiter.
ALIGN 2 Yes Control word (CW) for RX alignment.
EMPTY_CYC 2 Yes Empty cycle in a data transfer.
IDLE 1 No IDLE (out of band).
DATA 1 Yes Payload.
Table 10.  CW Field Description
Field Description
RSVD Reserved field. May be used for future extension. Tied to 0.
num_valid_bytes_eob Number of valid bytes in the last word (64-bit). This is a 3-bit value.
  • 3'b000: 8 bytes
  • 3'b001: 1 byte
  • 3'b010: 2 bytes
  • 3'b011: 3 bytes
  • 3'b100: 4 bytes
  • 3'b101: 5 bytes
  • 3'b110: 6 bytes
  • 3'b111: 7 bytes
EMPTY Number of non-valid words at the end of a burst.
eop Indicates the RX Avalon® streaming interface to assert an end-of-packet signal.
sop Indicates the RX Avalon® streaming interface to assert a start-of-packet signal.
seop Indicates the RX Avalon® streaming interface to assert a start-of-packet and an end-of-packet in the same cycle.
align Check RX alignment.
CRC32 The values of computed CRC.
usr Indicates that the control word (CW) contains user-defined information.

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