Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.5. Link Rate and Bandwidth Efficiency Calculation

The Serial Lite IV Intel® FPGA IP bandwidth efficiency calculation is as below:

Bandwidth efficiency = raw_rate * 64/66 * (burst_size - burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period - 2) / srl4_align_period]

Table 16.  Bandwidth Efficiency Variables Description
Variable Description
raw_rate This is the bit rate achieved by the serial interface.

raw_rate = SERDES width * transceiver clock frequency

Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps

burst_size

Value of burst size.

To calculate average bandwidth efficiency, use common burst size value.

For maximum rate, use maximum burst size value.

burst_size_ovhd The burst size overhead value.

In Full mode, the burst_size_ovhd value is referring to the START and END paired CWs.

In Basic mode, there is no burst_size_ovhd because there is no START and END paired CWs.

align_marker_period

The value of the period where an alignment marker is inserted.

The value is 81920 clock cycle for compilation and 1280 for fast simulation. This value is obtained from the PCS hard logic.
align_marker_width The number of clock cycles where a valid alignment marker signal is held high.
srl4_align_period The number of clock cycles between two alignment markers. You can set this value using the Alignment Period parameter in the IP Parameter Editor.

The link rate calculations are as below:

Effective rate = bandwidth efficiency * raw_rate

You can get the maximum user clock frequency with the following equation. The maximum user clock frequency calculation assumes continuous data streaming and no IDLE cycle occurs at the user logic. This rate is important when designing the user logic FIFO to avoid FIFO overflow.

Maximum user clock frequency = effective rate / 64

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