Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

5. Parameters

Table 20.  IP
Parameter Value Default Description
General Design Options
XCVR Mode
  • PAM4
  • NRZ
PAM4 Select the PCS modulation mode.
Number of lanes
  • For PAM4 mode:
    • 2
    • 4
    • 6
    • 8
  • For NRZ mode:
    • 1 to 16
2 Select the number of lanes.
Transceiver reference clock frequency
  • For PAM4 mode:
    • 156.25 MHz
    • 312.5 MHz
  • For NRZ mode:
    • 138.888888 MHz to 500 MHz
156.25 MHz Specifies the transceiver's reference clock frequency.
Preserve unused transceiver channels for PAM4

Enable

Disable

Disable Turn on to preserve unused transceiver channels for PAM4 mode.
Reference clock frequency for preserved channels 125 MHz to 500 MHz 156 MHz Set the clock frequency of reference clock for the unused preserved channels. If used, this value must be the same as the reference clock frequency that you set for other unused preserved channels in the same tile. This option is only applicable when you turn on Preserve unused transceiver channels for PAM4.
User Interface
Enable Auto Alignment

Enable

Disable

Disable Turn on to enable automatic lane alignment feature.
Enable RSFEC

Enable

Disable

Enable Turn on to enable the RS-FEC feature.

For PAM4 PCS modulation mode, RS-FEC is always enabled.

Enable CRC

Enable

Disable

Disable Turn on to enable CRC error detection and correction.
Alignment Period 128-65536 128 Specifies the alignment marker period.

The value must be x2.

Streaming Mode
  • Full
  • Basic
Full Select the data streaming for the IP.

Full: This mode sends a start-of-packet and end-of-packet cycle within a frame.

Basic: This is a pure streaming mode where data is sent without a start-of-packet, empty, and end-of-packet to increase bandwidth.

Transceiver data rate
  • For PAM4 mode:
    • 32.5 Gbps
    • 40.0 Gbps
    • 53.125 Gbps
    • 56.0 Gbps
  • For NRZ with RS-FEC disabled mode:
    • 9.92 Gbps to 28.0 Gbps
  • For NRZ with RS-FEC enabled mode:
    • 10.000 Gbps to 28.0 Gbps

53.125 Gbps (PAM4)

25.0 Gbps (NRZ)

Specifies the effective data rate at the output of the transceiver incorporating transmission and other overheads. The value is calculated by the IP by rounding up to 1 decimal place in Gbps unit.

IP Debug and Phy Dynamic Reconfiguration

Table 21.  Native Transceiver Phy
Parameter Value Default Description
Dynamic Reconfiguration
Enable dynamic reconfiguration Enable Turn on to enable dynamic reconfiguration interface of Transceiver Native PHY.
Enable Native PHY Debug Master Endpoint

Disable

Enable

Disable Turn on to enable the Native PHY Debug Master Endpoint and Optional Reconfiguration Logic Parameters of Transceiver Native PHY.
Optional Reconfiguration Logic
Enable capability registers

Disable

Enable

Disable Turn on to enable capability register of Transceiver Native PHY, which provide high level information about the transceiver PLL configuration.
Set user-defined IP identifier 0 Sets a user-defined numeric identifier that can be read from the user-identifier offset when the capability registers are enabled.

You must enable the Enable capability registers parameter to change the value for this parameter.

Enable control and status registers

Disable

Enable

Disable Turn on to enable control and status registers of Transceiver Native PHY.

For parameters in the PMA Adaptation tab, refer to the PMA Adaptation topic in the E-Tile Transceiver PHY User Guide.

Did you find the information on this page useful?

Characters remaining:

Feedback Message