Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.1.2.4. Empty-cycle CW

Figure 11. Empty-cycle CW Format

When you deassert tx_avs_valid for two clock cycles during a burst, the MAC inserts an EMPTY_CYC CW paired with END/START CWs. You can use this CW when there is no data available for transmission momentarily.

When you deassert tx_avs_valid for one cycle, the IP deasserts tx_avs_valid for twice the period of tx_avs_valid deassertion to generate a pair of END/START CWs.

Table 14.   EMPTY_CYC CW Field Values
Field Value
align 0
eop 0
sop 0
usr 0
seop 0

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