3.3. Serial Lite IV Intel® FPGA IP Clock Architecture
- Transceiver reference clock (xcvr_ref_clk)—Input clock from external clock chips or oscillators which generates clocks for TX MAC, RX MAC, and TX and RX custom PCS blocks. The IP supports reference clocks provided from separate clock chips or oscillators with a tolerance of ±100 ppm clock variation between the different clock chips or oscillators. Refer to Parameters for supported frequency range.
- TX core clock (tx_core_clk)—This clock is derived from transceiver PLL (clk_pll_div64[mid_ch]) in the custom PCS and is used for TX custom PCS interface and TX MAC. This clock is also an output clock from the IP to connect to the TX user logic.
- RX core clock (rx_core_clk)—This clock is derived from the transceiver PLL (clk_pll_div64[mid_ch]) in the custom PCS and is used for RX custom PCS interface, RX deskew FIFO, and RX MAC. This clock is also an output clock from the IP to connect to the RX user logic.
- Clock for transceiver reconfiguration interface (reconfig_clk)—input clock from external clock circuits or oscillators which generates clocks for custom PCS and RS-FEC reconfiguration interface in both TX and RX datapaths. The clock frequency is 100 to 162 MHz. For more about custom PCS and RS-FEC reconfiguration interface, refer to E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs.
The following block diagram shows Serial Lite IV Intel® FPGA IP clock domains and the connections within the IP.
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