Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

2. Serial Lite IV Intel® FPGA IP Overview

Serial Lite IV Intel® FPGA IP is suitable for high bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.

The Serial Lite IV Intel® FPGA IP incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block. The IP supports data transfer up to 56 Gbps per lane with a maximum of eight PAM4 lanes in a single link or 28 Gbps per lane with a maximum of 16 NRZ lanes. This protocol offers high bandwidth, low overhead frames, low I/O count, and supports high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-tile transceiver. It also supports reference clocks provided from separate clock chips or oscillators with a tolerance of ±100 ppm clock variation between the different clock chips or oscillators.

This IP supports two transmission modes:
  • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
  • Full mode—This is a packet transfer mode. In this mode, the IP sends a burst and a sync cycle at the start and end of a packet as delimiters.
Figure 1.  Serial Lite IV High Level Block Diagram

You can generate Serial Lite IV Intel® FPGA IP design examples to learn more about the IP features. Refer to Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide and Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide .

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