Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.1.3. TX CRC

You can enable the TX CRC block using the Enable CRC parameter in the IP Parameter Editor. This feature is supported in both Basic and Full modes.

The MAC adds the CRC value to the END CW by asserting the tx_avs_endofpacket signal. In the BASIC mode, only the ALIGN CW paired with END CW contains a valid CRC field.

The TX CRC block interfaces with the TX Control Word Insertion and TX MII Encode block. The TX CRC block computes the CRC value for 64-bit value per-cycle data starting from the START CW up to the END CW.

You can assert the crc_error_inject signal to intentionally corrupt data in a specific lane to create CRC errors.

Did you find the information on this page useful?

Characters remaining:

Feedback Message