Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

3.4.3. PMA Adaptation Flow

The PMA block in the Serial Lite IV Intel® FPGA IP uses the same PMA adaptation flow as the E-Tile Hard IP for Ethernet Intel® FPGA IP. Refer to the Ethernet Adaptation Flow with Non-external AIB Clocking section in E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs to trigger the PMA adaptation flow for the Serial Lite IV Intel® FPGA IP.

Table 15.  Signal Mapping Between Serial Lite IV Intel® FPGA IP and E-Tile Hard IP for Ethernet Intel® FPGA IP
Signal Name

(Serial Lite IV Intel® FPGA IP)

Equivalent Signal Name

(E-Tile Hard IP for Ethernet Intel® FPGA IP)

NRZ Mode (10GE/25GE) PAM4 Mode (100GE)
tx_pcs_fec_phy_reset_n i_sl_tx_rst_n i_tx_rst_n
rx_pcs_fec_phy_reset_n i_sl_rx_rst_n i_rx_rst_n
reconfig_reset i_reconfig_reset i_reconfig_reset

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