Serial Lite IV Intel® FPGA IP User Guide

ID 683655
Date 12/01/2021
Public
Document Table of Contents

7.2. Error Handling Guidelines

The following table lists the error handling guidelines for error conditions which may occur with the Serial Lite IV Intel® FPGA IP design.
Table 30.  Error Condition and Handling Guidelines
Error Condition Guidelines
One or more lanes cannot establish communication after a given time frame. Implement a time-out system to reset the link at the application level.
A lane loses communication after communication is established. This may happen after or during the data transfer phases. Implement a link loss detection at the application level and reset the link.
A lane loses communication during the deskew process. Implement link reinitialization process for the erroneous lane. You must ensure that the board routing does not exceed 320 UI.
Loss lane alignment after all lanes have been aligned. This may happen after or during data transfer phases. Implement a lane alignment loss detection at the application level to restart the lane alignment process.

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