Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

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ID 683619
Date 9/24/2018
Public
Document Table of Contents

1.11. Document Revision History

Date Version Changes
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
December 2014 14.1.0
  • Minimal text edits for clarity in the topic about understanding SSN.
June 2014 14.0.0 Updated format.
June 2012 12.0.0 Removed survey link.
November 2011 10.0.2 Template update
December 2010 10.0.1 Template update
July 2010 10.0.0
  • Reorganized and edited the chapter
  • Added links to Intel® Quartus® Prime Help for procedural information previously included in the chapter
November 2009 9.1.0
  • Added “Figure 6–9 shows the layout cross-section of a PCB in the Cadence Allegro PCB tool. The cross-section shows the stackup information of a PCB, which tells you the number of layers used in your PCB. The PCB shown in this example consists of various signal and circuit layers on which FPGA pins are routed, as well as the power and ground layers.” on page 6–12
  • Updated for the Intel® Quartus® Prime  software 9.1 release
March 2009 9.0.0 Initial release

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