Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents Updating IOPLL IP Design File Names

If you generate this design example and regenerate the four IOPLL IP components after generating this design example, the random string suffixes of the IOPLL IP component design file names may change.

To ensure proper simulation elaboration, follow these steps:

  1. Open the simulation script for the simulator of your choice.
    Simulator Simulator Script
    ModelSim* <Example Design>/example_testbench/setup_scripts/common/modelsim_files.tcl
    VCS* MX <Example Design>/example_testbench/setup_scripts/common/vcs_files.tcl
    VCS* MX <Example Design>/example_testbench/setup_scripts/common/vcsmx_files.tcl
    Xcelium* <Example Design>/example_testbench/setup_scripts/common/xcelium_files.tcl
  2. Edit the four IOPLL IP design files names in the simulation script to match with the regenerated IOPLL IP component design file names.
    Examples of the IOPLL IP design files names with random string suffix that need to be updated:
    • alt_core_iopll_tse_clk_altera_iopll_1931_oppet4q.vo
    • alt_core_iopll_tse_rx_clk_altera_iopll_1931_t57sz6i.vo
    • alt_core_iopll_upstream_altera_iopll_1931_4pedkla.vo
    • alt_tse_iopll_todsampling_clk_altera_iopll_1931_7vfkdfa.vo

    1931 is the IP version. oppet4q, t57sz6i, 4pedkla, and 7vfkdfa are the random strings that are specific to the Quartus version and IOPLL.

  3. Save the file.

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