Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
ID
683551
Date
4/30/2024
Public
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1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
2.2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Quartus® Prime Pro Edition software
- ModelSim* -SE, VCS* , VCS* MX, and Xcelium* simulators
- For hardware testing:
- Stratix® 10 TX Signal Integrity E-Tile Development Kit (1ST280EY2F55E2VG)
- QSFP-DD module for loopback