Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents

2.2.6. Interface Signals

Table 10.  Interface Signals for 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
Signal Direction Description
csr_clk Input 125 MHz input clock used for the control and status register (CSR) block of the IP, reference clock used for time-of-day (TOD) and deterministic latency (DL) IOPLL.
iopll_refclk Input 125 MHz input clock used as reference clock for RX IOPLL.
refclk_1g Input 156.25 MHz reference clock for E-tile transceiver Native PHY (PMA).
tx_serial_data Output Transmit serial data.
rx_serial_data Input Receive serial data.
channel_ready_n Output Channel ready status for TX and RX datapath.