Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Public
Document Table of Contents

1.2.4. Simulation

The testbench sends traffic using Traffic Controller in the TX direction of IP (consisting of the MAC and PCS) and looped back at the E-tile transceiver. The received traffic in the RX direction is monitored by the Traffic Controller. Avalon® streaming interface is used to transmit and receive data between the IP and client logic. Avalon® memory-mapped interface is used to access configuration and status registers.

Did you find the information on this page useful?

Characters remaining:

Feedback Message