Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents

1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver

Updated for:
Intel® Quartus® Prime Design Suite 21.2
IP Version 19.4.0

This design example demonstrates an Ethernet solution for Stratix® 10 E-tile devices using the Triple-Speed Ethernet IP. You can generate the design from the Example Design tab of the Triple-Speed Ethernet IP parameter editor.

To generate the design example, you must first set the parameter values for the IP variation you intend to generate in your end product. Generating the design example creates a copy of the IP. The testbench and hardware design example use the copy of the IP as the device under test (DUT). If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP variation that you intend.

  1. The testbench demonstrates a basic test of the IP. It is not intended to be a substitute for a full verification environment. You must perform more extensive verifications of your own Triple-Speed Ethernet design in simulation and in hardware.
  2. For Quartus® Prime Pro Edition software version 21.2, a patch is required to generate the 10/100/1000Mb Ethernet MAC (Fifoless) with 2XTBI PCS with E-Tile GXB Transceiver design example. Refer to KDB link: Why does the Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example generation fail? to download the patch.