Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Public
Document Table of Contents

2.2.7.4. TOD Register Map

Table 19.  TOD Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW SecondsH

Bits [15:0]: The upper 16 bits of the second field of TOD.

Bits [31:16]: Reserved.

0
0x04 RW SecondsL The lower 32 bits of the second field of TOD. 0
0x08 RW NanoSec The 32 bit nanosecond field of TOD. 0
0x10 RW Period The period for the frequency adjustment.

Bits [15:0]: The fractional nanosecond field.

Bits [19:16]: The nanosecond field.

Bits [31:20]: Reserved

0
0x14 RW AdjustPeriod

The offset adjustment period.

Bits [15:0]: The fractional nanosecond field.

Bits [19:16]: The nanosecond field.

Bits [31:20]: Reserved

0
0x18 RW AdjustCount

Bits [19:0]: The number of adjusted period in clock cycles.

Bits [31:20]: Reserved

0

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