Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683551
Date 10/21/2021
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.1.3.1. Procedure x
2.1.3.1.1. Updating IOPLL IP Design File Names
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.2.7.4. TOD Register Map

Table 19.  TOD Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW SecondsH

Bits [15:0]: The upper 16 bits of the second field of TOD.

Bits [31:16]: Reserved.

 0
0x04 RW SecondsL The lower 32 bits of the second field of TOD. 0
0x08 RW NanoSec The 32 bit nanosecond field of TOD. 0
0x10 RW Period The period for the frequency adjustment.

Bits [15:0]: The fractional nanosecond field.

Bits [19:16]: The nanosecond field.

Bits [31:20]: Reserved

 0
0x14 RW AdjustPeriod

The offset adjustment period.

Bits [15:0]: The fractional nanosecond field.

Bits [19:16]: The nanosecond field.

Bits [31:20]: Reserved

 0
0x18 RW AdjustCount

Bits [19:0]: The number of adjusted period in clock cycles.

Bits [31:20]: Reserved

 0
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