Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Public
Document Table of Contents

2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver

This design example demonstrates an Ethernet solution with deterministic latency (DL) feature for Intel® Stratix® 10 E-tile devices using the Triple-Speed Ethernet Intel® FPGA IP operating at 1G with timestamping and DL features enabled.

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