Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents Test Procedure

After you compile the Triple-Speed Ethernet Intel® FPGA IP design example and configure it on your Stratix® 10 device, you can use the System Console to program the IP.

Connect TX at terminal PIN_AU4 to RX at terminal PIN_AU10 of Stratix 10 TX Transceiver Signal Integrity Development Kit using the QSFP-DD loopback module.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Quartus® Prime Pro Edition software, select Tools > In-System Source and Probes Editor to open the default source and probe GUI.
  2. Select Device as indicated in In-System Sources and Probes Editor.
  3. Click File to select the .sof file and click Program Device.
  4. The initial value of source[0] is 0. Click on the value in the Data column to change the value to 1 to release the design from reset mode.
    Figure 9. In-System Sources and Probes Editor
  5. Once the design is out of reset, in the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools>System Console to launch the system console.
  6. In the Tcl Console pane, type cd hwtest/sc to change directory to <design_example_dir>/hardware_test_design/hwtest/sc/.
  7. Type source hwtest_main.tcl to run the design example in 10 Mbps, 100 Mbps and 1 Gbps Ethernet speed.
A successful test run displays the following message: