Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents

2.1.2. Generating the Design Example

Figure 12. Procedure to Generate Design Example
Figure 13. Example Design Tab in the Triple-Speed Ethernet Intel® FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
  2. Specify a specific Stratix® 10 device family that meets the following requirements:
    • Transceiver tile: E-tile
    • Transceiver speed grade: -1
    • Core speed grade: -1
  3. Click Finish to close the wizard.
  4. In the IP Catalog, locate and select Interface Protocol > Ethernet > 1G Multi-rate Ethernet > Triple-Speed Ethernet Intel FPGA IP. The New IP Variation window appears.
  5. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  6. Click OK. The parameter editors appears.
  7. On the Core Configurations, MAC Options, FIFO Options, Timestamp Options, and PCS/Transceiver Options tabs, specify the parameters for your IP variation. Refer to Design Components for the recommended parameters to generate the design example.
  8. On the Example Design tab, select 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver from Available Example Designs.
  9. For Example Design Files, select the Simulation option to generate the testbench, or the Synthesis option to generate the hardware design example.
    Note: You must select at least one of the options to generate the design example.
  10. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL.
    Note: If you select VHDL, you must simulate the testbench with a mixed language simulator. The device under test is a VHDL model, but the main testbench file is a System Verilog file.
  11. Under Target Development Kit, select the Stratix 10 TX Transceiver Signal Integrity Development Kit or select None.
    1. If you select a specific development kit as the Target Development Kit, the design example is generated based on the specific device and overwrites the device you selected in your project file.
    2. If you select None as the Target Development Kit, ensure that the selected device is your targeted device and adjust the pins assignment in the .qsf file. By default, the .qsf file is generated based on the device used in the development kit.
  12. Click the Example Design: “example_design” button. The Select Example Design Directory window appears.
  13. If you want to modify the design example directory path or name from the defaults displayed (eth_tse_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
    Note: You must perform the parameter settings based on the steps above to generate the design example.
  14. Click OK.