Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Document Table of Contents Design Example Parameters

Table 3.  Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings.
Example Design Files

The files to generate for the different development phase.

  • Simulation—generates the necessary files for simulating the example design.
  • Synthesis—generates the synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing and perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is not available, there is no supported board for the options that you select.

Stratix 10 TX Signal Integrity Development Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device.

No Development Kit: This option excludes the hardware aspects for the design example.