Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents Procedure

You can simulate the design by running a simulation script from the command prompt.
Note: You must perform an IOPLL IP upgrade for the 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE1588v2 and 2XTBI PCS with E-Tile GXB Transceiver design example. To generate the design example and regenerate the four IOPLL IP components, perform the steps in the Updating IOPLL IP Design File Names section. For more information, refer to KDB link: Why do I need to perform the IOPLL Intel® FPGA IP Upgrade in the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example?.

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench/<Simulator>.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Simulator Working Directory Command
    ModelSim* <Example Design>/example_testbench/mentor vsim -c -do
    VCS* <Example Design>/example_testbench/mentorsynopsys/vcs sh
    VCS* MX <Example Design>/example_testbench/synopsys/vcsmx sh
    Xcelium* <Example Design>/example_testbench/xcelium sh
A successful simulation ends with the following message:
Simulation passed.

After successful completion, you can analyze the results.

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