Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents

2.1.1. Directory Structure

The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files for the 10/100/1000Mb Ethernet MAC (Fifoless) design example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-tile GXB transceiver:
  • The compilation and hardware design example, hardware configuration, and test files are located in <design_example_dir>/hardware_test_design.
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
Figure 11. Directory Structure for the Design Example
Table 7.  Directory and File Description
Directory/File Description
altera_eth_top.qpf Intel® Quartus® Prime Pro Edition project file.
altera_eth_top.qsf Intel® Quartus® Prime Pro Edition settings file. Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
common The folder that contains the design example components such as address decoder and traffic controller.
ip The folder that contains the design example synthesizable components including Platform Designer generated IPs, such as TSE, IOPLL, Native PHY, and JTAG.
sc The folder that contains system console scripts for hardware testing.


Design example DUT top-level files.
output_files The folder that contains Intel® Quartus® Prime Pro Edition output files including Intel® Quartus® Prime Pro Edition compilation reports and design programing file (.sof file).
example_testbench/models The folder that contains the testbench files.




The folder that contains the simulation script. It also serves as a working area for the simulator.

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