Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents Testbench

Figure 7. Block Diagram of the 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver Simulation Testbench

A successful testbench sends ten packets and receives the same number of packets. The following sample output illustrates the excerpt of the output:

Figure 8. Simulation Test Result

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