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1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
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2.2.7.1. Register Access Definition
Access | Definition |
---|---|
RO | Read only. |
RW | Read and write. |
RWC | Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) upon executing the instruction. |
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