Triple-Speed Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 10/21/2021
Document Table of Contents

2.1. Quick Start Guide

The Triple-Speed Ethernet Intel® FPGA IP provides the capability of generating design examples for selected configurations, which allows you to:

  • Compile the design to get an estimate of the IP area usage and timing.
  • Simulate the design to verify the IP functionality through simulation.
  • Test the design on the hardware using the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 10. Development Stages for the Design Example

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